Integrated circuit memory devices are widely used in consumer and commercial applications. As is well known to those having skill in the art, integrated circuit memory devices include volatile and nonvolatile memory devices. Volatile memory devices may include Dynamic Random Access Memory (DRAM) devices and Static Random Access Memory (SRAM) devices. These volatile memory devices lose their data when their power supplies are interrupted. Nonvolatile memory devices may include Masked Read-Only Memory (MROM) devices, Programmable Read-Only Memory (PROM) devices, Erasable Programmable Read-Only Memory (EPROM) devices and Electrically Erasable Programmable Read-Only Memory (EEPROM) devices. These nonvolatile memory devices retain their stored data even when their power supplies are interrupted.
As is also well known to those having skill in the art, electrically erasable nonvolatile memory devices may include floating gate devices and charge trap devices. A floating gate electrically erasable nonvolatile memory device stores charges in an isolated floating gate. A charge trap electrically erasable nonvolatile memory device stores charges in traps in a charge trapping region. These technologies are generally described in Chapter 3.5 of the textbook entitled Semiconductor Memories: Technology, Testing, and Reliability by Ashok K. Sharma, 1997, pp. 104-116, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein. As described therein, charge trap nonvolatile memory devices (also called charge trap EEPROMs) also may be referred to as Metal Nitride Oxide Silicon (MNOS) or (poly)Silicon Oxide Nitride Oxide Semiconductor (SONOS) devices based on the gate structures thereof.
Since the floating gate device stores charges as free carriers, all stored data may be lost if a tunnel oxide layer thereof is even partially defective. In contrast, since the charge trap device stores charges in spatially isolated traps in the charge trapping region, stored data may not be entirely lost even when a tunnel oxide layer is partially defective. Therefore, the tunnel oxide layer of a charge trap memory device may be made thinner than that of a floating gate memory device. Operational voltages of charge trap nonvolatile memory devices therefore may be lower than those of floating gate nonvolatile memory devices.
As is well known to those having skill in the art, a charge trap electrically erasable nonvolatile memory cell generally includes a transistor in an integrated circuit substrate. The transistor includes a gate having a charge trapping region therein. More specifically, the transistor may include spaced apart source and drain regions in an integrated circuit substrate, and a gate on the integrated circuit substrate therebetween. The gate may include a tunnel insulating layer on the substrate, a charge trapping region on the tunnel insulating layer, a blocking insulating layer on the charge trapping region, and a gate electrode on the blocking insulating layer.
As is well known to those having skill in the art, operation of nonvolatile memory devices can include a program operation, an erase operation and a read operation. These operations will be described with reference to FIG. 1 which graphically illustrates drain current (Id) and gate voltage (VG) for a conventional electrically erasable charge trap nonvolatile memory cell. In particular, an electrically erasable charge trap nonvolatile memory cell has an initial property that is defined by the relationship between the drain current and the gate voltage, as shown by curve 11 of FIG. 1. An initial threshold voltage VTi of the memory cell may be defined from the curve 11.
The memory cell is initially programmed, for example, by applying a voltage of 0V to the substrate, and applying a program voltage higher than 0V to the gate electrode. As a result, electrons in a channel area between the source and drain regions are injected into deep-level traps through the tunnel insulating layer. Once programmed, the programmed cell has a predefined relationship between the drain current and the gate voltage, as shown by curve 12. As shown in FIG. 1, curve 12 is shifted towards positive gate voltage compared to curve 11. Curve 12 defines a program threshold voltage VTP that is higher than the initial threshold voltage VTi.
In order to erase the programmed or unprogrammed cell, a reference voltage is applied to the substrate and an erase voltage, which is lower than the reference voltage, is applied to the gate electrode. As a result, electrons trapped in the charge trapping region are injected into the substrate through the tunnel insulating layer. Holes in the substrate also may be injected into the traps in the charge trapping region through the tunnel insulating layer. As shown in FIG. 1, an erased cell defines a relationship between the drain current and the gate voltage thereof, as shown by curve 13 of FIG. 1. This curve is shifted toward a negative gate voltage (−V). Thus, an erased cell has an erase threshold voltage VTe that is lower than the initial threshold voltage VTi and which may be a negative voltage.
Programming and erasing of floating gate EEPROMs are described in U.S. Pat. No. 6,483,752 to Hirano; U.S. Pat. No. 6,442,075 to Hirano; U.S. Pat. Nos. 6,261,884; 6,347,053 to Kim et al.; U.S. Pat. No. 6,261,884 to Ho et al.; U.S. Pat. No. 6,188,609 to Sunkavalli et al.; U.S. Pat. No. 6,169,693 to Chan et al.; U.S. Pat. No. 6,160,740 to Cleveland; U.S. Pat. No. 6,054,732 to Ho et al.; U.S. Pat. No. 6,026,026 to Chan et al.; U.S. Pat. Kaida et al.; U.S. Pat. No. 5,790,460 to Chen et al.; and U.S. Pat. No. 5,699,298 to Shiau et al. Moreover, programming and erasing of electrically erasable charge trap nonvolatile memory cells are described in U.S. Pat. No. 6,490,205 to Wang et al.; U.S. Pat. No. 6,418,062 to Hayashi et al.; U.S. Pat. No. 6,266,281 to Derhacobian et al.; and U.S. Pat. No. 5,999,444 to Fujiwara et al.
It is well known that the erase operation can impact the endurance of the electrically erasable charge trap nonvolatile memory cell by attacking the interface between the substrate and the tunnel insulating layer during the erase operation, which may create interface traps. These interface traps may deteriorate the endurance and/or speed of an electrically erasable charge trap nonvolatile memory cell.